宇航计测技术 ›› 2013, Vol. 33 ›› Issue (3): 28-33.doi: 10.12060/j.issn.1000-7202.2013.03.06

• 论文 • 上一篇    下一篇

一种适于GNSS信号快捕的FFT核的设计与实现

汤震武1；盛利元1；杨俊2   

  1. 1、中南大学 物理与电子学院，湖南长沙 410083；
    2、国防科技大学机电工程与自动化学院，湖南长沙 410073
  • 出版日期:2013-06-15 发布日期:2013-06-15

Design and Implement of FFT Core Applying to the Fast Acquisition of GNSS Signal

TANG Zhen-wu1；SHENG Li-yua1；YANG Jun2   

  1. 1、College of Physics and Electronics, Central South University, Changsha, Hunan 410083;
    2、College of Mechatronics Engineering and Automation, National University of Defense Technology, Changsha, Hunan 410073
  • Online:2013-06-15 Published:2013-06-15

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摘要： 针对GNSS信号捕获的要求，在Quartus II 7.2集成开发环境下，采用Verilog HDL语言，设计了一种256点复数基2时间抽取FFT处理器。利用Matlab工具联合Quartus II进行仿真，提高仿真效率，并最后进行硬件测试。结果表明，本文设计的FFT处理器具有较小的面积和较高的处理速度，能够满足GNSS接收机信号处理的要求。

关键词: 快速傅里叶变换, 现场可编程门阵列, 联合仿真, Verilog HDL语言

Abstract: With the requirements of fast acquisition of GNSS signal, a FFT processor of radix-2 with 256 points complex input is designed in this paper. The FFT core was designed with Verilog HDL language under the Quartus II 7.2, and in order to improve the simulation efficiency, Matlab is used to simulate together with Quartus. Finally a test was done on the design and the result shows that the FFT processor designed in the paper has less resource consumption and higher processing speed, meeting the basic requirement of GNSS receivers.

Key words: FFT, FPGA, Co-Simulation, Verilog HDL

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