Abstract: With the requirements of fast acquisition of GNSS signal, a FFT processor of radix-2 with 256 points complex input is designed in this paper. The FFT core was designed with Verilog HDL language under the Quartus II 7.2, and in order to improve the simulation efficiency, Matlab is used to simulate together with Quartus. Finally a test was done on the design and the result shows that the FFT processor designed in the paper has less resource consumption and higher processing speed, meeting the basic requirement of GNSS receivers.

Key words: FFT, FPGA, Co-Simulation, Verilog HDL